The present invention relates in general to computer system architectures and more particularly to a method and apparatus for decoupling processor speed from memory subsystem speed in a node controller.
Existing computer systems typically operate at processor speed that is a multiple of the processor system bus. The processor system bus is the communication link between the processor and a node controller in the computer system. The node controller interfaces the processor with a memory that operates at its own speed, typically at a different speed than the processor. The node controller typically has the same operating speed as the memory. Generally, the processor system bus clock is derived from the operating clock of the node controller, either the same as or a divided down version of the node controller""s clock. Because the clock of the node controller has some ratio relationship to a speed of the processor, independent scaling of the processor and the node controller of memory cannot be accomplished. As processor roadmaps extend for many generations scaling up in frequencies, conventional computer system designs do not have the capability to adjust for changes in frequencies of processors with respect to their memories and node controllers. Therefore, it is desirable to provide a computer system where the speed of a processor is not derived or dependent of a speed of its node controller or memory.
From the foregoing, it may be appreciated that a need has arisen for a technique to decouple the processor""s frequency from a core frequency of its memory and associated node controller. In accordance with the present invention, an apparatus and method of decoupling processor speed from memory subsystem speed in a node controller are provided which substantially eliminate or reduce disadvantages and problems associated with conventional computer system designs.
According to an embodiment of the present invention, there is provided a method of decoupling processor speed from memory subsystem speed of a node controller that includes receiving data from a processor and writing the data into a buffer of a crossbar unit in the node controller in response to a clock rate of the processor system bus. The data is read from the buffer in response to a clock rate of the crossbar unit. Data is written into the buffer by latching a write address of a buffer location with the clock rate of the processor. The write address is then passed to crossbar unit of the node controller by successive latching of the write address according to a clock rate of the node controller. A read address is generated according to the clock rate of the node controller in response to the write address. The data is read out of the buffer, which was written into the buffer at the speed of the processor system bus, at the speed of the crossbar unit.
The present invention provides various technical advantages over conventional computer system designs. For example, one technical advantage is to decouple the speed of the processor from the speed of its associated memory and node controller. Another technical advantage is the ability to have the processor clock domain be slower than, equal to, or faster than the core clock domain of the node controller. Yet another technical advantage is to synchronize the transfer of data using two different clock speeds. Still another technical advantage is to synchronize write addresses used to write data into a buffer at a first clock speed to form a read address to read data from the buffer at a second clock speed. Other technical advantages may be readily apparent to those skilled in the art from the following figures, description, and claims.